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Lattice Semiconductor
Table 1-8. CIC Filter IP Core for LatticeXP2 Devices Quick Facts
CIC IP Configuration
Introduction
Decimator with rate
is 48 and data with is
8 and stage is 4
Decimator with rate
is 4096 and data with
is 16 and stage is 8
Interpolator with rate
is 35 and data with is
15 and stage is 7
Core ?
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Lattice XP2
LFXP2-5E
LFXP2-17E-7F484C
Resource ?
Utilization
LUTs
sysMEM EBRs
Registers
221
0
301
1594
0
1253
985
0
1982
Lattice Implementation
Diamond 1.0 or ispLEVER 8.1
Design Tool ?
Support
Synthesis
Simulation
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Mentor ModelSim SE 6.3F
Features
? 1-32-bit input data width
? 1-8 cascaded stages
? 1-4 cycles differential delay, run-time programmable for both decimation and interpolation
? 2-16,384 decimation and interpolation sampling rate factor, run-time programmable rates for both decimation
and interpolation
? Multi-channel (up to 40 channels) support for both decimation and interpolation
? Fully synchronous, single-clock design
IPUG42_02.6, August 2010
8
Cascaded Integrator-Comb (CIC) Filter User’s Guide
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